This relates generally to communications links, and more particularly, to high-speed input-output (I/O) communications links.
A typical communications link includes a transmitter, a receiver, and a channel that connects the transmitter to the receiver. The transmitter transmits a serial data bit stream to the receiver via the channel. Typical high-speed transmit data rates are 1 Gbps (gigabits per second) to 10 Gbps. Communications links operating at such high data rates are often referred to as high-speed serial links or high-speed input-output links.
Typically, the transmitter outputs the data bits at periodic intervals using a transmitter clock signal with 50% duty cycle while the receiver latches incoming serial data bits using data latching circuits. The receiver may include clock data recovery (CDR) circuitry that generates a clock signal having transitions aligned to the center of each data bit (i.e., the clock signal has rising and falling edges centered within each data bit window).
Centering the clock signal transitions within each data bit window may be desirable if the setup and hold time requirements associated with the data latching circuits are equal. In practice, however, the setup and hold time requirements are often different. For example, consider a scenario in which a pre-charge sense amplifier circuit in a data latching circuit exhibits a setup time that is substantially less than its hold time. In this scenario, positioning the clock edges at the center of each data window would be inefficient as some timing margin would be wasted in the hold region. As another example, consider a scenario in which the receive data bits exhibit a distorted data eye that is skewed towards the right. In this scenario, positioning the clock edges at the center of the distorted data eye would also be inefficient as some timing margin would be wasted in the setup region.